Code That Performs and Outperforms — Prepare for the Performance Requirements of Tomorrow

Learn how to harness the power and performance of Intel® technologies in your compute intense applications—for free. Seats are limited to get the latest developments in Intel tools and technologies that can make your applications work better, faster and smarter. 2017 Intel® Software Developer Conference is a one day technical training. Don’t miss the opportunity to share best practices and techniques to help realize the full potential of today and tomorrow’s compute environment.

Register today to:

  • Learn how to modernize existing or new code to maximize performance on current and future Intel® Xeon® and Intel® Xeon Phi™ processors
  • Gain deep insights into the latest programming techniques and tools for achieving the highest performance on Intel® architecture with C / C ++ or Fortran
  • Accelerate your machine learning performance with a faster Python
  • Get the latest tuning methodologies and techniques for a wide variety of Intel embedded/IoT platforms
  • Learn about the latest in high performance computing, numerical simulation, analytics, and artificial intelligence from Intel experts
  • And much more

Register here ›

When:
December 5, 2017
Where:

Westhafen Pier 1 GmbH
Rotfeder -Ring 1
60327 Frankfurt am Main
Conference Suite – Upper Floor

December 5, 2017

8:00 - 9:30
Registration
9:30 - 10:00
Intel Keynote Ways to Achieve Peak Performance on Intel® Hardware

High-performance doesn’t just happen. To unlock the power of modern high-performance computers, software needs to be designed with modern coding techniques vectorization, multithreading, memory optimization, and more. In this information-packed session, Jim will discuss how to optimize performance on the extensive variety of Intel® hardware, including an introduction to the latest innovations in code modernization tools and techniques that are helping developers achieve peak performance on Intel® hardware.

Jim Cownie
Jim Cownie
About the Speaker

Jim Cownie is an ACM Distinguished Engineer and Intel Principal Engineer. He has been involved with parallel computing since starting to work for Inmos in 1979. Along the way he owned the profiling chapter in the MPI-1 standard and has worked on parallel debuggers and OpenMP implementations. If he wasn't here, he would rather be skiing.

10:00 - 10:45
Latest Intel hardware roadmap for technical computing
Stephan Gillich
Stephan Gillich
About the Speaker

Stephan Gillich is Director of Technical Computing, Analytics and Artificial Intelligence - GTM for Intel EMEA Datacenter Group - Intel Deutschland GmbH. His responsibilities include the positioning of Intel products and solutions in the High Performance Computing (HPC), Analytics and Artificial Intelligence environment. Together with his cross-site and inter-organizational team, Stephan Gillich plans and implements strategies for the European region and the Middle East. Stephan Gillich joined Intel as a Computer Scientist in the Supercomputing Division.
Since then, he has gained comprehensive expertise on clients and servers in numerous business areas and he has held various management positions with responsibility for technology and the positioning and marketing of relevant products for businesses, industries and end-users. As a member of the steering committee of the Digital Video Broadcasting Project (DVB) he has also worked towards the expansion of unified standards in the media industry. Stephan Gillich holds a degree (Dipl. Inform. univ.) in Computer Science from the Technische Universität München.

10:45 - 11:00
Break
11:00 - 11:45
Optimizing for Latest Processors with Intel® Parallel Studio XE 2018

Come learn how to modernize your code for Performance, Portability and Scalability on the Latest Intel® Platforms. In particular, this talk will cover

  • Intel® Advanced Vector Extensions 512 (Intel® AVX-512) instructions on - Intel® Xeon® and Intel® Xeon® Phi™ processors and coprocessors
  • Intel® Advisor - Roofline finds high impact, but under optimized loops
  • Intel® Distribution for Python* - Faster Python* applications
  • Application Performance Snapshot – Get quick answers: Does my hybrid code need optimization?
  • Intel® VTune™ Amplifier – Profile private clouds with Docker* and Mesos* containers, Java* daemons
Heinrich Bockhorst
Heinrich Bockhorst
About the Speaker

Heinrich received a PhD in Solid State Physics. He is currently a Senior Technical Consultant for HPC in the Software and Services Group. He supports several Intel Parallel Compute Centers in their code modernization efforts. His primary interests include MPI/Hybrid applications and related analyzing tools.

11:45 - 12:30
Intel® Distribution for Python* – Advantages and Acceleration

Python is a popular open source scripting language known for its easy to learn syntax and an active developer community.  Performance, however, remains a key drawback due to Python being an interpreted language and the implementation of the GIL lock. The Intel® Distribution for Python* is an easy to install, optimized Python Distribution that includes the popular NumPy & SciPy stack packages used for scientific, engineering and data analysis. The Distribution tunes and leverages the powerful Intel® Math Kernel Library to offer significant performance gains, enhancing the performance profile of your application. For example, DGEMM functions deliver 3x speedups on single core and show impressive scalability on multiple cores. The Distribution’s easy out-of-the box installation saves you time and effort, so even a novice Python user can focus on the application at hand, rather than setting up the Python infrastructure

 Frank Schlimbach
 Frank Schlimbach
About the Speaker

Frank Schlimbach currently works with Intel/SSG as a Software Architect on scripting languages and tools. Since his PhD he worked on parallel, distributed and performance oriented software. Among others, he developed distributed load balancing algorithms, parallel programming models and tools for performance analysis of parallel and distributed programs.

12:30 - 13:15
Lunch Break
13:15 - 14:00
Intel Compilers for HPC – Overview and Latest Advancements

A simple way to boost performance is to augment your development process with an Intel® C++ and Fortran Compilers.
Intel compilers produce optimized code that can run significantly faster by taking advantage of the ever increasing core count and vector register width in Intel and compatible processors.

We will talk about new compiler features supporting new processors, latest Fortran 2008, C++17 and OpenMP 5.0 standards, optimizations for Intel® Advanced Vector Extensions 512 (Intel® AVX-512), Parallel STL and many other features helping you deliver fast, reliable, scalable parallel code with 18.0 compiler.

Fabio Baruffa
Fabio Baruffa
About the Speaker

Fabio Baruffa is a Technical Consulting Engineer for HPC in Intel's Software and Services Group. Prior to Intel, he worked for several years as an HPC Application Specialist in the largest supercomputing centers in Europe, mainly Leibniz Supercomputing Center and Max-Plank Computing and Data Facility in Munich as well as Cineca in Italy – where he was involved in software development, analysis of scientific code and optimization for HPC systems. He holds a PhD in Physics from University of Regensburg for his research in the area of Spintronics device and quantum computing.

14:00 - 14:45
Latest Advances in High Performance Libraries

This presentation will cover the latest advances in threading and performance libraries:

  • Intel® IPP is an extensive library which includes thousands of optimized functions covering frequently used fundamental algorithms including those for creating digital media, enterprise data, embedded, communications, and scientific/technical applications
  • Intel® Math Kernel Library (Intel® MKL) optimizes code with minimal effort for future generations of Intel processors. It is compatible with your choice of compilers, languages, operating systems, and linking and threading models. It features highly optimized, threaded, and vectorized math functions that maximize performance on each processor family.
  • Intel® Threading Building Blocks (Intel® TBB) lets you easily write parallel C++ programs that are portable, composable, and have future-proof scalability.
Fabio Baruffa
Fabio Baruffa
About the Speaker

Fabio Baruffa is a Technical Consulting Engineer for HPC in Intel's Software and Services Group. Prior to Intel, he worked for several years as an HPC Application Specialist in the largest supercomputing centers in Europe, mainly Leibniz Supercomputing Center and Max-Plank Computing and Data Facility in Munich as well as Cineca in Italy – where he was involved in software development, analysis of scientific code and optimization for HPC systems. He holds a PhD in Physics from University of Regensburg for his research in the area of Spintronics device and quantum computing.

14:45 - 15:30
Intel® VTune™ Amplifier XE for Tuning of HPC Applications

We will explore the special VTune Amplifier profiling capabilities for HPC and will highlight new features and use cases for the latest processors.
In particular, we will cover the following topics

  • The “Memory Access” analysis which helps tracking down various memory-related issues
  • The HPC Performance Characterization analysis preview providing application efficiency hints like memory bound metric and FPU utilization
  • Hybrid MPI + OpenMP analysis
  • Disk I/O analysis delivering a new storage analysis which is the first step in order to support 3D Xpoint™ technology
Klaus-Dieter Oertel
Klaus-Dieter Oertel
About the Speaker

Klaus-Dieter Oertel is a Senior Technical Consultant for HPC in Intel's Software and Services Group. He belongs to the first generation of parallelization experts in Germany and worked on all kinds of supercomputers. Klaus-Dieter supports several Intel Parallel Computing Centers in their code modernization efforts targeting parallelism on all system levels from processes, over threads, to vectors.

15:30 - 15:45
Break
15:45 - 16:30
HPC code optimization and modernization efforts at Max Planck Gesellschaft

The Max Planck Computing and Data Facility (MPCDF) is a cross-institutional competence center of the Max Planck Society to support computational and data sciences.
The MPCDF operates a state-of-the-art supercomputer, several mid-range compute clusters and data repositories, and provides an up-to-date infrastructure for data management and long-term archival.
This talk will focus on high-performance-computing (HPC) activities at the MPCDF, specifically on the co-development and optimization of leading HPC applications from various scientific domains. We shall present a number of case studies and highlight our experiences and insights gained from recent code-modernization projects.

Markus Rampp from Max Planck Gesellschaft
Markus Rampp from Max Planck Gesellschaft
About the Speaker

Dr. Markus Rampp is the head of the high-performance computing (HPC) applications group of the Max Planck Computing and Data Facility (MPCDF). He received a diploma in physics (1997) and a PhD in Natural Sciences (2000, awarded with the Otto-Hahn medal of the Max Planck Society), both from the Technical University of Munich. After working as a pre and postdoctoral researcher in computational astrophysics at the Max Planck Institute for Astrophysics (1997-2003) he joined the RZG (predecessor of the MPCDF), where he has been leading software development and support for computational biology applications (awarded with the Heinz-Billing award for the advancement of scientific computation, 2004), scientific visualization (since 2008), and HPC application support (since 2010).

16:30 - 17:15
Visualizing and Finding Optimization Opportunities with Intel® Advisor Roofline feature

An Intel Advisor Roofline Analysis provides insight into:

  • Where your performance bottlenecks are
  • How much performance is left on the table because of them
  • Which bottlenecks are possible to address, and which ones are worth addressing
  • Why these bottlenecks are most likely occurring
  • What your next steps should be

While the Roofline chart is not a conversion table that directly tells you exactly what changes need to be made in your code, it is an incredibly useful diagnosis tool. Examples will be shown that best demonstrate best practices with this new cutting

Klaus-Dieter Oertel
Klaus-Dieter Oertel
About the Speaker

Klaus-Dieter Oertel is a Senior Technical Consultant for HPC in Intel's Software and Services Group. He belongs to the first generation of parallelization experts in Germany and worked on all kinds of supercomputers. Klaus-Dieter supports several Intel Parallel Computing Centers in their code modernization efforts targeting parallelism on all system levels from processes, over threads, to vectors.

17:15 - 18:00
Enabling the Future of Artificial Intelligence

Artificial intelligence is unlocking tremendous economic value across various market sectors. Individual data scientists can draw from several open source frameworks and basic hardware resources during the very initial investigative phases but quickly require significant hardware and software resources to build and deploy production models. Intel offers various hardware to support a diversity of workloads and user needs. Intel built a competitive deep learning platform to make it easy for data scientists to start from the iterative, investigatory phase and take models all the way to deployment. This platform is designed for speed and scale, and serves as a catalyst for all types of organizations to benefit from the full potential of deep learning. Example of supported applications include but not limited to automotive speech interfaces, image search, language translation, agricultural robotics and genomics, financial document summarization, and finding anomalies in IoT data. This talk will detailed what Intel has done and plans to do from hardware to software to state-of-the-art algorithms in order to democratized AI.

Jacek Czaja
Jacek Czaja
About the Speaker

Jacek Czaja is a Machine Learning engineer in Intel Artificial Intelligence Product Group (AIPG) solutions enablement team. He is responsible for enabling and optimizing AI solutions into Intel platforms. He is a computer scientist with a passion for applicable machine learning. Prior to joining Intel he worked as Developer Technology engineer at Imagination Technologies. He got his M.Eng. from Gdansk University of Technology.

18:00 - 19:00
Closing and Networking